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LDS8866
BLOCK DIAGRAM
Figure 2. LDS8866 Functional Block Diagram
BASIC OPERATION
At power-up, PWM1 and PWM2 pins should be logic
LOW. During power-up device performs internal
circuits reset that requires less than 10μs. To start
device either PWM1 or PWM2 pin should be set logic
HIGH 10μs after than input voltage applied. Device
starts operating at 1-x mode at which the output is
approximately equal to the input supply voltage (less
any internal voltage losses). If the output voltage is
sufficient to regulate all LED currents, the device
remains in 1-x operating mode.
The low dropout PowerLite ? Current regulator
(PCR) performs well at input voltages Vin up to
75 mV above LED forward voltage V F significantly
increasing driver’s efficiency. The LDS8866 monitors
voltage drop Vd across PCR at every channel in ON
state. If this voltage falls below 75 mV (typical) at any
one channel, (channel with LED with highest forward
voltage), the Mode Control Block changes charge
pump mode to the next multiplication ratio.
Vd = V IN x M – V F – Rcp x Iout, where Rcp is a
Charge Pump Output Resistance at given mode, Iout
is sum of all LED currents, and M is a charge pump’
multiplication ratio.
If the input voltage is insufficient or falls to a level
where Vd ≤ 75 mV, and the regulated currents cannot
be maintained, the low dropout PowerLite ? Current
Regulator switches the charge pump into 1.33-x
mode (after a fixed delay time of about 800 μ s). In
1.33-x mode, the charge pump’ output voltage is
approximately equal to 1.33 times the input supply
voltage (less any internal voltage losses).
This sequence repeats at every mode until driver
enters the 2-x mode.
If the device detects a sufficient input voltage is
present to drive all LED currents in 1-x mode, it will
change automatically back to 1-x mode. This only
applies for changing back to the 1-x mode. The
difference between the input voltage when exiting 1-x
? 2009 IXYS Corp.
Characteristics subject to change without notice
6
Doc. No. 8866DS, Rev. N2.0
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